The performance of transistor devices often depends on the behavior of electrons, or electron holes, traveling from one portion of the transistor device to another. For example, parameters such as the gain or the linearity of a heterojunction bipolar transistor (HBT) may depend on the capacitance between the base and the collector of the bipolar transistor. Parasitic capacitance between the base and the collector would degrade the performance of the heterojunction bipolar transistor.
In the prior art, attempts have been made to improve the performance of bipolar transistors. For example, U.S. Pat. No. 5,672,522 discloses an HBT in which the sub-collector area is selectively ion-implanted. FIG. 1 shows the cross-sectional image of a GaAs-based HBT with a selectively silicon (Si) implanted sub-collector 54 fabricated on a semi-insulating GaAs substrate 50, upon which a collector 61, a base 58, and an emitter 60 are formed, with a base ohmic metal 62 on the base 58, and an emitter ohmic metal 64 on the emitter 60. In a first method, the sub-collector area 54 was defined by a typical Si-ion implantation on the selective area. The ion implantation process was followed by collector, base and emitter epitaxial growth. In a second method, oxygen ion implantation was executed on the pre-grown Si doped sub-collector region 54. The oxygen implanted area turns out to be highly resistive. However, in the device in FIG. 1, only the sub-collector area was reduced. In addition, a selective N+ sub-collector area was defined by ion implantation, which may cause ion damage, and in turn the ion damage may result in degrading crystal quality of the followed layers.
Also in the prior art, as shown in FIG. 2, U.S. Pat. No. 5,981,985 discloses an HBT in which overlapping is minimized between the base 13 and sub-collector region 11. FIG. 2 is a cross-sectional image of GaAs HBT with a selectively buried sub-collector 11, a collector 12, a base 13, an emitter 14, metals 25-27, and passivation elements 30. The sub-collector region 11 is defined by photolithography. The reduced sub-collector 11 is used as a template for the subsequent epitaxial growth. The subsequently fabricated collector, base and emitter layers conformally form on the top of the substrate 10. Most of the collector, base and emitter regions is etched off to minimize the area overlapping between collector 12 and sub-collector 11, which results in a significant reduction of the base-collector capacitance Cbc. However, in the device in FIG. 2, performance was limited or reduced since only the sub-collector area was reduced, and the layout for the device stacks was not properly organized since epitaxial overgrowth for device stacks was not planarized.
Also, in the prior art, known HBT structures have layouts where the sub-collector area is greater than the base area, such as shown in FIG. 4A, while the collector area is the same as the base area. A few different methodologies have been proposed in the prior art to reduce the parasitic base-collector capacitance Cbc. A significant reduction of the capacitance Cbc allows for the fabrication of HBTs to boost up the speed of HBTs and improve their linearity. As shown in FIGS. 1-2, different device layouts have been implemented to decrease the base-collector capacitance Cbc. The two devices in FIGS. 1-2 use a reduced sub-collector region that is heavily Si doped. However, such prior art devices still suffer from the effects of excessive base-collector capacitance Cbc and the resulting poor gain and poor linearity of such prior art devices.